Current technology trends continue to focus on high performance CMOS (complementary metal-oxide-semiconductor) and a new arena of VLSI (very-large-scale integration) called Smart Power chips is being developed. Smart Power chips are built with both low and high voltage CMOS. Power transistors (e.g. the high voltage CMOS) on these Smart Power chips typically allow operating voltages up to 40 volts. The thrust of current research focuses on improving the high voltage transistor performance.
Smart Power chips are widely used in the automotive industry. The automotive environment is harsh and requires relatively high levels of protection against ESD and other types of transients. However, power transistors are generally weak for ESD due to their inherent device structure. Good ESD performance actually requires low power dissipation capability under high currents. This is inherent in optimized thin oxide nMCOS transistor structures, but not in high voltage power transistors. The thin-oxide nMOS transistor inherently includes a lateral npn formed of the drain (collector), substrate (base) and source region (emitter). This lateral npn provides excellent ESD protection by efficiently dissipating the ESD event. However, for the typical high voltage transistor, such as the DENMOS (drain extended NMOS), lateral bipolar action is difficult to initiate or turn-on.
A prior-art DEMMOS power transistor is shown in FIG. 1. The DENMOS is built in a p-tank 112 located in a p-type epitaxial substrate 110. The drain 116 is formed in a n-well 114. The source 118 is formed directly in the stank 112 The gate 120 is located partially over the stank and partially over a field oxide region 122 that is located between the drain 116 and the source 118. A 500 .ANG. gate oxide 124 is located between the gate 120 and the stank 112 Typical channel lengths (between the source 118 edge and the n-well 114 edge) are on the order of 5 .mu.m. This is too long for the inherent bipolar device to turn-on during an ESD event. Instead, during ESD, the n-tank at the drain gets fully depleted and the device operates as a vertical diode dissipating the current through the substrate. However, this creates a high field at the thin oxide below the gate before the ESD event is dissipated that can often damage the device. Therefore, there is a need for a high voltage transistor having improved ESD protection capability.